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mrkrad

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Posts posted by mrkrad

  1. Thanks, is it possible to reduce the clock rates for the P states? The problem with fermi quadro (4,5,6000) not K series, is that the virtual svga api-intercept for esxi - if you don't generate a consistent load you are stuck near max P state, thus making it so slow to ramp up that software renderer is better.

    Is there an easy way to bop the steps so it is very aggressive except for the maximum power savings state?

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