Tri-harder

@Nando Is it possible to add additional BCLKs to setPLL for a supplied definition PLL? The provided definition .lut file for ics9LPRS387bklf BCLKs start at 266 and go through 357. Unfortunately that’s too high for my use. I need it to start at BLCK of 200. How can I add BCLK 200 to 265? Edit: never mind, I now understand after looking further into the lut file. Background: I have an Acer eMachines E725-4520, PLL, GL40 chipset & T4400 x11 800MHz FSB CPU. I just recently completed a PLL hardware mod to enable TME (pin #14 to gnd via 10K resistor). I used the freeware setFSB with the PLL diagnosis clock generator (9LPRS387 is not supported) to manually set the registers as shown by Dufus here: M11x clock generator ICS9LPRS387BKLF - Page 12 I was able to increase BCLK from 200 to 217MHz, going any higher I get a white screen. Trying for a higher OC, I then increased the CPU voltage via a CPU pin mod of +.1V, which I confirmed by the moderate increased heat. But again a white screen at 217Mhz with no improvement in BCLK. Memory is not the issue either as mem peaks at 433Mhz with this small OC and current SPD memory timings of 6-6-6-18 at the lowest JEDEC of 457MHz 6-6-6-18, so plenty of room. In an attempt to achieve a higher OC and bypass setFSB incase I was doing something wrong there, I attempted an FSLx PLL pin mod from 200 to 266 by disconnecting the CPU and MCH from the PLL on pin #2 (FSLB) and then connecting pin #2 to gnd. GL40 only supports 667/800FSB. But I was in hopes this would allow me to trick the CPU and Chipset to 266Mhz. However, it would not POST, so I backed it out. I’m not sure what the limiting factor is in both instances, maybe it’s the GL40 chipset..? Any help would be appreciated as I’m trying to stretch the life of this laptop.